Buses and Memory Hierarchy

Dan · Dec 2, 2008

In this problem, you will answer questions about the memory system that is described below, compute the maximum (and minimum) memory latencies for a sequence of memory operations, and consider prefetching strategies that will decrease the latency to memory.

System specification:
• The processor operates on 4-byte values and stalls (waits) on load instructions. When a load is issued,
the processor holds until the requested value is available to be stored into the specified register. The
processor does not stall on store instructions.
• If a requested address is in the L1 cache, a load takes 8 processor cycles. The L1 cache starts empty
and stores the last 4 distinct “lines” of memory that were loaded. Addresses that are stored into are not
stored in the cache. Each line is 16 bytes long, so a line contains 4 4-byte values, and the cache contains
16 4-byte values.
• If the address is not in the L1 cache, the load must come from memory. Then, the load takes 128 processor
cycles to complete. Instead of sending only the requested value, however, each load returns the 16-byte
line in which the requested address is found.

Answer each of the following questions about the memory system described above.

1. If the memory contains 64k bytes and each byte can be addressed, how large is an address?

2. How many bits are required to specify a particular word from a line of memory?

3. How many bits are required to specify which line of memory is being requested?

4. Each load that is sent to memory reserves the bus for the entire 128 cycles. Each store takes 64 cycles.
Since stores do not stall the processor, memory requests are “packaged” together: we wait until a load is
received or until the bus is fully utilized before sending the memory requests all at once.
Assume that the bus is 16 bytes wide so that it can transmit a line of memory in one shot. How many
memory requests can be packaged and sent to the memory at the same time?
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anyone who has taken computer organization before, please explain to me this lol

Buses and Memory Hierarchy

Dan 8-D